Complete the design review details below Save at any time using the button at the bottom of the form. Step 1 of 10 10% Product DetailsThe details below give a general overview of the product reviewed in this report. Product Name PCB Part Number PCB Revision TechnologyFill out the details below regarding the board technology and specifications. Board Material Min Track/Gap Clearance Number of Layers Min Via Size Surface Finish Max Voltage PCB StackupThe table below is used to show the stackup composition of your PCB. You should be able to view the data for this directly in your PCB design tool or alternatively use your gerber files.Enter Detail of Each PCB Layer BelowLayerTypeThicknessUsage Layer type should be specified as: SM = Â Â Solder mask P = Â Â Â Pre-preg C = Â Â Â Â Â Core R = Â Â Â Â Â Copper layer used for routing RP = Â Â Copper layer used for routing & placement P = Â Â Â Â Â Copper layer used as plane/pour R+P = Copper layer used for routing + pourUsage should be specified as: H = Horizontal routing layer V = Vertical routing layer H&V = Routing layer for both horizontal & vertical Or insert Net name for planes Radiated & Conducted Emission LimitsEnter details about the radiated and conducted emission limits that apply to your product below. Check your product standards for the data. If unsure, request a test plan from your local EMC test house. These limits represent the performance specification that your product must meet in terms of EMI.Which emissions tests are applicable to your product? Radiated emissions AC conducted emissions DC conducted emissions Flicker and harmonic emissions Magnetic Field Standards, frequency bands and limitsRadiated EmissionsStandardPortFreq. RangeLimitClass Example: Standard: FCC 15.209 Port: Enclosure Freq Range: 30 MHz - 80 MHz Limit: 100 uV/m Class: BAC Conducted EmissionsStandardPortFreq. RangeLimitClass Example: Standard: FCC 15.107 Port: AC input Freq Range: 150 kHz - 500 kHz Limit: 66 to 56 (QP) Class: BDC Conducted EmissionsStandardPortFreq. RangeLimitClass Voltage Flicker & Harmonic CurrentStandardPortFreq. RangeLimitClass Magnetic FieldStandardPortFreq. RangeLimitClass Additional Notes (For Report) Power and Ground Nets and Copper Planes/PoursReviewing all ground and power nets in the design helps the reviewer to visualize where and how power is flowing around the design.List the main power and ground nets used in the circuit:Net NameDescriptionImplementationLayer(s)Source Net Name: e.g. GND Description: Describe the function of the net. e.g. Digital ground Implementation: e.g. Plane/pour/routed Layer(s): Layers where net is present. e.g. 1,3,4 Source: e.g. Star point - near supplyAdditional Notes (For Report) Power Supplies and DecouplingListing all of the power supplies and reference nets helps the reviewer visualize power connectivity, return paths and how the power is flowing through the design. The maximum current draw helps to show which power supplies may be worth spending more time analyzing. Also include supplies that are derived from other supplies through a filter (such as analog or RF supplies). Include any findings in the notes section below.List the power supplies used in the applicationNet NameReference NetVoltageMax. CurrentRegulator Type Additional Notes (For Report)Check For Each Power SupplyIf voltage regulator is on board, specify type (linear / switching) and reference designator. If voltage regulator is external, specify type and approximate cable length Number of Power Supplies*Please enter a number from 0 to 10.Enter the number of internal and external voltage regulators in your design. This will enable the correct number of checkboxes below.Reference designator A filter is provided The filter is placed near the voltage regulator, or voltage entry point if regulator is external The filter uses a capacitor for low-frequency filtering The filter uses a capacitor for high-frequency filtering Input current loop minimized Verify current path Verify voltage distribution point Ground is low impedance Reference designator A filter is provided The filter is placed near the voltage regulator, or voltage entry point if regulator is external The filter uses a capacitor for low-frequency filtering The filter uses a capacitor for high-frequency filtering Input current loop minimized Verify current path Verify voltage distribution point Ground is low impedance Reference designator A filter is provided The filter is placed near the voltage regulator, or voltage entry point if regulator is external The filter uses a capacitor for low-frequency filtering The filter uses a capacitor for high-frequency filtering Input current loop minimized Verify current path Verify voltage distribution point Ground is low impedance Reference designator A filter is provided The filter is placed near the voltage regulator, or voltage entry point if regulator is external The filter uses a capacitor for low-frequency filtering The filter uses a capacitor for high-frequency filtering Input current loop minimized Verify current path Verify voltage distribution point Ground is low impedance Reference designator A filter is provided The filter is placed near the voltage regulator, or voltage entry point if regulator is external The filter uses a capacitor for low-frequency filtering The filter uses a capacitor for high-frequency filtering Input current loop minimized Verify current path Verify voltage distribution point Ground is low impedance Reference designator A filter is provided The filter is placed near the voltage regulator, or voltage entry point if regulator is external The filter uses a capacitor for low-frequency filtering The filter uses a capacitor for high-frequency filtering Input current loop minimized Verify current path Verify voltage distribution point Ground is low impedance Reference designator A filter is provided The filter is placed near the voltage regulator, or voltage entry point if regulator is external The filter uses a capacitor for low-frequency filtering The filter uses a capacitor for high-frequency filtering Input current loop minimized Verify current path Verify voltage distribution point Ground is low impedance Reference designator A filter is provided The filter is placed near the voltage regulator, or voltage entry point if regulator is external The filter uses a capacitor for low-frequency filtering The filter uses a capacitor for high-frequency filtering Input current loop minimized Verify current path Verify voltage distribution point Ground is low impedance Reference designator A filter is provided The filter is placed near the voltage regulator, or voltage entry point if regulator is external The filter uses a capacitor for low-frequency filtering The filter uses a capacitor for high-frequency filtering Input current loop minimized Verify current path Verify voltage distribution point Ground is low impedance Reference designator A filter is provided The filter is placed near the voltage regulator, or voltage entry point if regulator is external The filter uses a capacitor for low-frequency filtering The filter uses a capacitor for high-frequency filtering Input current loop minimized Verify current path Verify voltage distribution point Ground is low impedance Additional Notes (For Report) Supply Sensitive BlocksSupply sensitive blocks are those that are particularly susceptible to noise and power supply ripple. Extra care is required with these power supplies to avoid issues occurring with the supply sensitive circuitry. Typical supply sensitive blocks include sensitive analog circuity and RF transmitter/receivers. Number of Supply Sensitive Blocks*Please enter a number from 0 to 10.Enter the number of supply sensitive blocks/rails in your design. This will enable the correct number of checkboxes below.Block/power rail identifier A filter is provided Check for proximity to aggressor nets Check for proximity to potentially noisy power supplies Block/power rail identifier A filter is provided Check for proximity to aggressor nets Check for proximity to potentially noisy power supplies Block/power rail identifier A filter is provided Check for proximity to aggressor nets Check for proximity to potentially noisy power supplies Block/power rail identifier A filter is provided Check for proximity to aggressor nets Check for proximity to potentially noisy power supplies Block/power rail identifier A filter is provided Check for proximity to aggressor nets Check for proximity to potentially noisy power supplies Block/power rail identifier A filter is provided Check for proximity to aggressor nets Check for proximity to potentially noisy power supplies Block/power rail identifier A filter is provided Check for proximity to aggressor nets Check for proximity to potentially noisy power supplies Block/power rail identifier A filter is provided Check for proximity to aggressor nets Check for proximity to potentially noisy power supplies Block/power rail identifier A filter is provided Check for proximity to aggressor nets Check for proximity to potentially noisy power supplies Block/power rail identifier A filter is provided Check for proximity to aggressor nets Check for proximity to potentially noisy power supplies Block/power rail identifier A filter is provided Check for proximity to aggressor nets Check for proximity to potentially noisy power supplies Enter Notes For The Report HerePower and Ground Pours/PlanesComplete the details below regarding any power/ground planes or copper pours. The configuration of planes/pours can have a large impact on aspects related to EMI performance such as inter-plane capacitance, PDN impedance, return paths, current loops, signal impedance and transient immunity performance. Note any issues found in the notes section below.Enter number of separate ground/power pours/planes in the design*Please enter a number from 0 to 10.Design does not use pours/planes so this section is empty.Power/Ground Plane/Pour Name Adjacent planes have at least 0.5mm clearance Same net planes on different layers are stitched using vias at 10mm spacing Check for plane islands and stubs RF/analog supply planes are given extra clearance RF/analog supply planes are provided with inductors to adjacent same-net planes Power/Ground Plane/Pour Name Adjacent planes have at least 0.5mm clearance Same net planes on different layers are stitched using vias at 10mm spacing Check for plane islands and stubs RF/analog supply planes are given extra clearance RF/analog supply planes are provided with inductors to adjacent same-net planes Power/Ground Plane/Pour Name Adjacent planes have at least 0.5mm clearance Same net planes on different layers are stitched using vias at 10mm spacing Check for plane islands and stubs RF/analog supply planes are given extra clearance RF/analog supply planes are provided with inductors to adjacent same-net planes Power/Ground Plane/Pour Name Adjacent planes have at least 0.5mm clearance Same net planes on different layers are stitched using vias at 10mm spacing Check for plane islands and stubs RF/analog supply planes are given extra clearance RF/analog supply planes are provided with inductors to adjacent same-net planes Power/Ground Plane/Pour Name Adjacent planes have at least 0.5mm clearance Same net planes on different layers are stitched using vias at 10mm spacing Check for plane islands and stubs RF/analog supply planes are given extra clearance RF/analog supply planes are provided with inductors to adjacent same-net planes Power/Ground Plane/Pour Name Adjacent planes have at least 0.5mm clearance Same net planes on different layers are stitched using vias at 10mm spacing Check for plane islands and stubs RF/analog supply planes are given extra clearance RF/analog supply planes are provided with inductors to adjacent same-net planes Power/Ground Plane/Pour Name Adjacent planes have at least 0.5mm clearance Same net planes on different layers are stitched using vias at 10mm spacing Check for plane islands and stubs RF/analog supply planes are given extra clearance RF/analog supply planes are provided with inductors to adjacent same-net planes Power/Ground Plane/Pour Name Adjacent planes have at least 0.5mm clearance Same net planes on different layers are stitched using vias at 10mm spacing Check for plane islands and stubs RF/analog supply planes are given extra clearance RF/analog supply planes are provided with inductors to adjacent same-net planes Power/Ground Plane/Pour Name Adjacent planes have at least 0.5mm clearance Same net planes on different layers are stitched using vias at 10mm spacing Check for plane islands and stubs RF/analog supply planes are given extra clearance RF/analog supply planes are provided with inductors to adjacent same-net planes Power/Ground Plane/Pour Name Adjacent planes have at least 0.5mm clearance Same net planes on different layers are stitched using vias at 10mm spacing Check for plane islands and stubs RF/analog supply planes are given extra clearance RF/analog supply planes are provided with inductors to adjacent same-net planes Enter Notes For The Report Here Power Supplies and Decoupling Continued...This section deals with power and ground track routing. Note any issues found in the notes section below.Enter number of separate power/ground nets in the design*Please enter a number from 0 to 10.This refers to ground and power nets that are routed as traces rather than pours/planes.Power/ground Net Name Trace is as wide as PCB allows (check current reqs.) Trace and return path are close as possible Star topology is used where possible for both ground and power traces Clearance is maximized to adjacent supplies Power/ground Net Name Trace is as wide as PCB allows (check current reqs.) Trace and return path are close as possible Star topology is used where possible for both ground and power traces Clearance is maximized to adjacent supplies Power/ground Net Name Trace is as wide as PCB allows (check current reqs.) Trace and return path are close as possible Star topology is used where possible for both ground and power traces Clearance is maximized to adjacent supplies Power/ground Net Name Trace is as wide as PCB allows (check current reqs.) Trace and return path are close as possible Star topology is used where possible for both ground and power traces Clearance is maximized to adjacent supplies Power/ground Net Name Trace is as wide as PCB allows (check current reqs.) Trace and return path are close as possible Star topology is used where possible for both ground and power traces Clearance is maximized to adjacent supplies Power/ground Net Name Trace is as wide as PCB allows (check current reqs.) Trace and return path are close as possible Star topology is used where possible for both ground and power traces Clearance is maximized to adjacent supplies Power/ground Net Name Trace is as wide as PCB allows (check current reqs.) Trace and return path are close as possible Star topology is used where possible for both ground and power traces Clearance is maximized to adjacent supplies Power/ground Net Name Trace is as wide as PCB allows (check current reqs.) Trace and return path are close as possible Star topology is used where possible for both ground and power traces Clearance is maximized to adjacent supplies Power/ground Net Name Trace is as wide as PCB allows (check current reqs.) Trace and return path are close as possible Star topology is used where possible for both ground and power traces Clearance is maximized to adjacent supplies Power/ground Net Name Trace is as wide as PCB allows (check current reqs.) Trace and return path are close as possible Star topology is used where possible for both ground and power traces Clearance is maximized to adjacent supplies Return PathsNon-ideal return paths can be a major source of signal integrity and radiated emissions problems. In this section, we investigate signals and their corresponding reference planes to ensure that the return paths are well defined. Instructions: Within your layout editor or gerber viewer, view 2 adjacent layers at a time to visualize the signal and return paths. Identify any signals that cross a plane slot or plane boundary and verify whether that plane is being used as a return path for the signal. If it is, either suggest a modification to the signal route/layer or plane area or bridge the return path with a decoupling capacitor to provide a low impedance return path for the RF current. Additionally, if a signal changes layer, the return path may change to a different reference layer. Bypass capacitors between reference planes may be needed to avoid creating a current loop in the return path. Enter any findings in the notes section below. Enter number of planes to check*Please enter a number from 0 to 10.Plane/pour Net Name Ensure signals do not cross slots in plane Bridging capacitor provided if signal traverses slot Bridging capacitor provided if signal changes reference plane Ensure signals do not exceed reference plane boundary Plane/pour Net Name Ensure signals do not cross slots in plane Bridging capacitor provided if signal traverses slot Bridging capacitor provided if signal changes reference plane Ensure signals do not exceed reference plane boundary Plane/pour Net Name Ensure signals do not cross slots in plane Bridging capacitor provided if signal traverses slot Bridging capacitor provided if signal changes reference plane Ensure signals do not exceed reference plane boundary Plane/pour Net Name Ensure signals do not cross slots in plane Bridging capacitor provided if signal traverses slot Bridging capacitor provided if signal changes reference plane Ensure signals do not exceed reference plane boundary Plane/pour Net Name Ensure signals do not cross slots in plane Bridging capacitor provided if signal traverses slot Bridging capacitor provided if signal changes reference plane Ensure signals do not exceed reference plane boundary Plane/pour Net Name Ensure signals do not cross slots in plane Bridging capacitor provided if signal traverses slot Bridging capacitor provided if signal changes reference plane Ensure signals do not exceed reference plane boundary Plane/pour Net Name Ensure signals do not cross slots in plane Bridging capacitor provided if signal traverses slot Bridging capacitor provided if signal changes reference plane Ensure signals do not exceed reference plane boundary Plane/pour Net Name Ensure signals do not cross slots in plane Bridging capacitor provided if signal traverses slot Bridging capacitor provided if signal changes reference plane Ensure signals do not exceed reference plane boundary Plane/pour Net Name Ensure signals do not cross slots in plane Bridging capacitor provided if signal traverses slot Bridging capacitor provided if signal changes reference plane Ensure signals do not exceed reference plane boundary Plane/pour Net Name Ensure signals do not cross slots in plane Bridging capacitor provided if signal traverses slot Bridging capacitor provided if signal changes reference plane Ensure signals do not exceed reference plane boundary Plane/pour Net Name Ensure signals do not cross slots in plane Bridging capacitor provided if signal traverses slot Bridging capacitor provided if signal changes reference plane Ensure signals do not exceed reference plane boundary Enter Notes For The Report Here IC DecouplingThis section ensures that you have included adequate decoupling for all ICs in your designThis section ensures that you have included adequate decoupling for all ICs in your designEnter Number of ICs to Review*Please enter a number from 1 to 20.IC Reference Designator Check all VCC/GND pairs At least one decoupling capacitor is provided Capacitors are located very close to ground or power pins Power/GND connections to IC are routed indirectly, through the decoupling capacitor IC to capacitor traces provide low impedance (short and wide) Capacitor to plane traces are short, with vias very close IC Reference Designator Check all VCC/GND pairs At least one decoupling capacitor is provided Capacitors are located very close to ground or power pins Power/GND connections to IC are routed indirectly, through the decoupling capacitor IC to capacitor traces provide low impedance (short and wide) Capacitor to plane traces are short, with vias very close IC Reference Designator Check all VCC/GND pairs At least one decoupling capacitor is provided Capacitors are located very close to ground or power pins Power/GND connections to IC are routed indirectly, through the decoupling capacitor IC to capacitor traces provide low impedance (short and wide) Capacitor to plane traces are short, with vias very close IC Reference Designator Check all VCC/GND pairs At least one decoupling capacitor is provided Capacitors are located very close to ground or power pins Power/GND connections to IC are routed indirectly, through the decoupling capacitor IC to capacitor traces provide low impedance (short and wide) Capacitor to plane traces are short, with vias very close IC Reference Designator Check all VCC/GND pairs At least one decoupling capacitor is provided Capacitors are located very close to ground or power pins Power/GND connections to IC are routed indirectly, through the decoupling capacitor IC to capacitor traces provide low impedance (short and wide) Capacitor to plane traces are short, with vias very close IC Reference Designator Check all VCC/GND pairs At least one decoupling capacitor is provided Capacitors are located very close to ground or power pins Power/GND connections to IC are routed indirectly, through the decoupling capacitor IC to capacitor traces provide low impedance (short and wide) Capacitor to plane traces are short, with vias very close IC Reference Designator Check all VCC/GND pairs At least one decoupling capacitor is provided Capacitors are located very close to ground or power pins Power/GND connections to IC are routed indirectly, through the decoupling capacitor IC to capacitor traces provide low impedance (short and wide) Capacitor to plane traces are short, with vias very close IC Reference Designator Check all VCC/GND pairs At least one decoupling capacitor is provided Capacitors are located very close to ground or power pins Power/GND connections to IC are routed indirectly, through the decoupling capacitor IC to capacitor traces provide low impedance (short and wide) Capacitor to plane traces are short, with vias very close IC Reference Designator Check all VCC/GND pairs At least one decoupling capacitor is provided Capacitors are located very close to ground or power pins Power/GND connections to IC are routed indirectly, through the decoupling capacitor IC to capacitor traces provide low impedance (short and wide) Capacitor to plane traces are short, with vias very close IC Reference Designator Check all VCC/GND pairs At least one decoupling capacitor is provided Capacitors are located very close to ground or power pins Power/GND connections to IC are routed indirectly, through the decoupling capacitor IC to capacitor traces provide low impedance (short and wide) Capacitor to plane traces are short, with vias very close Enter Notes For The Report HereGlobal Decoupling CapacitorsThis section relates to distributed decoupling capacitor placement across the circuit board. Decoupling capacitors placed between all adjacent plane pairs within X grid density Integrated Circuit ConfigurationThis section covers several aspects of IC selection that can affect EMI performance. Check all ICs for the following attributes Surface mount where possible (avoid TH components) Pick the lowest speed part necessary for design If I/O driver strength is configurable, set to minimum that design will allow Check all unused pins are tied high or low Enter Notes For The Report HereShieldingIf there are any shields in the design (e.g. LCD, RF module, analog zone), list them here and check the following details:Number of shields used in design*Please enter a number from 0 to 5.Shield Identifier Check the following attributes: Shield is grounded Shield is grounded at multiple points Shield is flush to board (no gaps) Check for dry solder joints Shield slots minimized Shield slots located away from noisy circuitry Shield Identifier Check the following attributes: Shield is grounded Shield is grounded at multiple points Shield is flush to board (no gaps) Check for dry solder joints Shield slots minimized Shield slots located away from noisy circuitry Shield Identifier Check the following attributes: Shield is grounded Shield is grounded at multiple points Shield is flush to board (no gaps) Check for dry solder joints Shield slots minimized Shield slots located away from noisy circuitry Shield Identifier Check the following attributes: Shield is grounded Shield is grounded at multiple points Shield is flush to board (no gaps) Check for dry solder joints Shield slots minimized Shield slots located away from noisy circuitry Shield Identifier Check the following attributes: Shield is grounded Shield is grounded at multiple points Shield is flush to board (no gaps) Check for dry solder joints Shield slots minimized Shield slots located away from noisy circuitry Enter Notes For The Report HereEnclosureDoes the product include an enclosure? Yes No Is enclosure conductive? Yes No If the equipment chassis is conductive, check the following details: Housing is used for shielding Low impedance connection to board ground at all mounting holes Include optional populated 1206 0 Ohm resistor at all mounting holes between chassis ground and board ground Ensure all I/O connector shields are tightly connected to enclosure with 360 degree low impedance bond (remove non-conductive coating if necessary) Ensure all parts of enclosure are electrically connected with low impedance (remove non-conductive coating if necessary) Enter Notes For The Report HereCablingThese guidelines apply more to large equipment where cable placement can make a big difference to radiated and conducted emissions. For each cable in your product, check the following details:Cable nameClassTypeClearance to other classesRuns close to ground conductorShort as possible Enter Notes For The Report HereCable ShieldingCable shielding can be included to reduce emissions from cabling. If you have chosen to included shielded cables for any external interfaces in your design, check the following detail for each cable:Port NameIs shield grounded?Grounded at both endsEnsure there are no pigtails Enter Notes For The Report HerePDN Impedance PlotIf the PCB stack-up includes pairs of adjacent power-ground planes, those will create a distributed capacitance that should be accounted for the power distribution network (PDN) impedance analysis. PDN Impedance Plot PDN Impedance Plot Provided Would you like to continue on to the high speed design review? Enable high speed design review Recommended for designs that feature edge rates of approx 3ns or shorter. High Speed Design ReviewThe definition 'high speed' (see armstrong, EMC for PCBs, page 8) Signal Reference RulesSignal reference rules refer to critical signals (definition) and their return paths. Critical net/bus nameNo crossing of split in reference plane (Y/N)No change in reference plane (Y/N)Not close to edge of reference plane (Y/N) Enter Notes For The Report HereRouting and Crosstalk RulesSignal reference rules refer to critical signals (definition) and their return paths. Critical net/bus nameNot routed within X distance from an I/O net (Y/N)Buried between solid planes (Y/N)Isolated from other nets by Y distance (Y/N) Enter Notes For The Report HereDifferential Routing RulesSignal reference rules refer to critical signals (definition) and their return paths. Does the design contain any differential pairs? Yes No Diff pair nameReturn vias placed symmetricallyDiff pairs routed within X distance of each otherLength of diff pair mates within Y skew Enter Notes For The Report HereDecoupling RulesThis section covers board level decoupling.Decoupling rules Decoupling capacitors placed between all adjacent plane pairs within X grid density Check all IC decoupling capacitors are placed within Y distance Check track between decoupling capacitor pad to power/ground reference via is less than Z distance Placement RulesThis section covers placement of I/O filtering and IC zoning.Placement rules Filters placed close to I/O connector pins that they are filtering Analog and digital circuitry are placed more than X distance apart CPU/FPGA/ASIC are place more than Y distance from I/O signals Congratulation on finishing the EMC radiated emissions design review! Enter your email address below to receive a PDF copy of the review.Email* Enter the email address (design review will be emailed to here) Δ
